One embodiment of the present invention relates to a programmable device for increasing memory cell and memory architecture design yield. More specifically, one embodiment of the present invention relates to block redundancy adapted to increase design yield in memory architecture.
Memory architectures typically balance power and device area against speed. High-performance memory architectures place a severe strain on the power and area budgets of the associated systems, particularly where such components are embedded within a VLSI system, such as a digital signal processing system for example. Therefore, it is highly desirable to provide memory architectures that are fast, yet power- and area-efficient.
Highly integrated, high performance components, such as memory cells for example, require complex fabrication and manufacturing processes. These processes may experience unavoidable parameter variations which may impose physical defects upon the units being produced, or may exploit design vulnerabilities to the extent of rendering the affected units unusable, or substandard.
In memory architectures, redundancy may be important, as a fabrication flaw or operational failure in the memory architecture may result in the failure of that system. Likewise, process invariant features may be needed to insure that the internal operations of the architecture conform to precise timing and parameter specifications. Lacking redundancy and process invariant features, the actual manufacturing yield for particular memory architecture may be unacceptably low.
Low-yield memory architectures are particularly unacceptable when embedded within more complex systems, which inherently have more fabrication and manufacturing vulnerabilities. A higher manufacturing yield of the memory cells may translate into a lower per-unit cost, while a robust design may translate into reliable products having lower operational costs. Thus, it is highly desirable to design components having redundancy and process invariant features wherever possible.
The aforementioned redundancy aspects of the present invention may can render the hierarchical memory structure less susceptible to incapacitation by defects during fabrication or operation, advantageously providing a memory product that is at once more manufacturable, cost-efficient, and operationally more robust.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.